Hardware ASIC Packaging SI/PI Simulation and Design Lead at Cisco · United States · Joined
C
Hardware ASIC Packaging SI/PI Simulation and Design Lead
Cisco · United States · Just now · 0 applicants
NewHybridFull-timeLead
Pay
$187k–$268kListed
Workplace
Hybrid
Job type
Full-time
Level
Lead
Source: jobright · Posted by joined-scrapper
About the role
Cisco is seeking a technical lead to own signal and power integrity analysis and ASIC package design for next-generation platforms. The role involves SI/PI simulation, layout validation, and mentoring while collaborating with layout teams and technical partners.
What you’ll do
Develop, define, design, and verify ASIC packaging for next-generation Cisco platforms
Lead SI/PI analysis and package design
Collaborate with layout teams and technical partners
Mentor engineers
Advance design processes and quality
What you’ll need
Bachelor's degree in Electrical Engineering and 8+ years relevant signal/power integrity experience (or Master's + 6 years, or PhD + 3 years)
Experience with high-speed design principles: transmission line theory, electromagnetics, scattering parameters, impedance network analysis, 56G PAM4 SerDes, channel modeling, and BER prediction
Experience with pre/post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience with layout reviews and physical design validation using Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Experience with HBM/high-speed memory interface, die-to-die interfaces (UCIe/proprietary), advanced packaging (CoWoS/EMIB/interposer), VNA, and IBIS
Original job description
Cisco is seeking a Signal and Power Integrity Technical Lead to develop, define, design, and verify ASIC packaging for next-generation Cisco platforms. The role leads SI/PI analysis and package design, collaborates with layout teams and technical partners, and mentors engineers while advancing design processes and quality.Bachelor's degree in Electrical…