DFT Engineer at Katalyst CRO · San Jose, CA · Joined
KC
DFT Engineer
Katalyst CRO · San Jose, CA · Just now · 0 applicants
NewOn-siteFull-timeMiddle
Pay
Pay not listed
Workplace
On-site
Job type
Full-time
Level
Middle
Source: jobright · Posted by joined-scrapper
About the role
The DFT Engineer will handle design-for-test and ATPG for SoC/ASIC designs, covering scan, MBIST, IO, and clock DFT. The role requires 4+ years of hands-on experience and expertise with industry-standard DFT/ATPG EDA tools.
What you’ll do
Implement design-for-test (DFT) for SoC/ASIC designs
Generate, analyze, and debug ATPG patterns
Support MBIST memory test architectures and diagnostics
Validate IO test methodologies for interface and pin-level testing
Perform clock DFT and clock verification
Support silicon bring-up and production test
What you’ll need
4+ years of hands-on DFT and ATPG experience for SoC/ASIC designs
Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
Proven expertise in ATPG pattern generation, analysis, and debug
Experience with MBIST, memory test architectures, and diagnostics
Knowledge of IO Test methodologies and clock DFT concepts
B-Tech, BE, or equivalent degree in Electronics domain
Original job description
The hiring company is confidential. The DFT Engineer role focuses on design-for-test and ATPG for SoC or ASIC designs, including scan testing, MBIST, IO testing, and clock DFT.4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designsStrong understanding of DFT fundamentals, including controllability, observability, and scan-based testing…