Senior RTL Design Engineer at Efficient Computer · San Francisco, CA · Joined
EC
Senior RTL Design Engineer
Efficient Computer · San Francisco, CA · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
$180k–$245kListed
Workplace
On-site
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
Efficient Computer is hiring a Senior RTL Design Engineer to design, integrate, and sign off RTL blocks for its power-efficient SoC, covering compute-fabric interconnects, memory interfaces, low-power logic, and peripheral IP through tapeout. The role requires deep front-end digital design experience and cross-functional collaboration.
What you’ll do
Design, integrate, and sign off RTL for SoC blocks
Develop compute-fabric interconnects, memory interfaces, and peripheral IP
Implement low-power RTL techniques (clock gating, power domains)
Run RTL simulations and debug with waveform tools
Work with cross-functional teams from microarchitecture to tapeout
Document designs and participate in design reviews
What you’ll need
8-10 years of front-end digital design experience on processor, accelerator, or SoC products
Significant contributions to at least two tapeout cycles
Strong proficiency in SystemVerilog for synthesizable RTL
Experience with low-power RTL techniques (UPF, clock gating, power domains, retention)
Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, NoC) at RTL level
Original job description
Efficient Computer is hiring a Senior RTL Design Engineer to design, integrate, and sign off RTL for blocks across its power-efficient SoC. The role spans compute-fabric interconnects, memory interfaces, low-power logic, and peripheral IP, working with cross-functional teams from microarchitecture through tapeout.8-10 years of front-end digital design…