ASIC Engineer, Performance Architecture and Modeling (University Grad) at Meta · Sunnyvale, CA · Joined
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ASIC Engineer, Performance Architecture and Modeling (University Grad)
Meta · Sunnyvale, CA · Just now · 0 applicants
NewOn-siteFull-timeJunior
Pay
Pay not listed
Workplace
On-site
Job type
Full-time
Level
Junior
Team: Silicon Engineering · Source: jobright · Posted by joined-scrapper
About the role
Meta is hiring a university-grad ASIC engineer to work on performance architecture and modeling for custom silicon in its Silicon Engineering organization. The role involves pre-silicon modeling, microarchitectural exploration, and performance analysis of custom ASICs for AI and data center workloads.
What you’ll do
Drive architectural performance analysis of custom ASICs
Perform pre-silicon modeling and microarchitectural exploration
Develop modeling methodologies, workloads, and roadmap strategy
Partner with architecture, design, and software teams
What you’ll need
Currently pursuing or has a BS/MS/PhD in CS, CE, EE, or relevant field, completing before joining
Proficiency in C++ and Python for simulation models, automation frameworks, and performance analysis tools
Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation
Experience with cycle-accurate or transaction-level performance models using C++ and SystemC
Experience analyzing data center, AI accelerator, or HPC workloads on custom silicon
Experience developing Python automation pipelines for simulation orchestration and regression testing
Original job description
Meta's Silicon Engineering organization builds custom silicon for its AI and data center infrastructure. The ASIC Engineer will drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs, while developing modeling methodologies, workloads, and roadmap strategy in partnership with architecture, design,…