RTL Engineer at DensityAI · Mountain View, CA · Joined
D
RTL Engineer
DensityAI · Mountain View, CA · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
$215k–$300kListed
Workplace
On-site
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
DensityAI is hiring an RTL Engineer to design and implement digital blocks for its AI accelerator. The role owns RTL from microarchitecture through synthesis-ready, timing-clean implementation and works closely with verification, physical design, DFT, and silicon bring-up teams.
What you’ll do
Own RTL development from microarchitecture through synthesis-ready implementation
Implement timing-clean digital blocks
Collaborate with design verification, physical design, and DFT teams
Support silicon bring-up
Write synthesizable RTL and SDC constraints
Automate design flows with scripting
What you’ll need
5+ years designing complex digital blocks or SoCs taken to silicon
Strong digital-design fundamentals
Expert Verilog/SystemVerilog RTL skills
Solid microarchitecture skills for pipelining, datapath/control, FIFOs, arbitration, memory subsystems, and NoC
Synthesis and timing awareness including SDC, STA, clock/power gating, CDC, and lint
Work authorization required at start
Original job description
DensityAI is developing an AI accelerator and is seeking an RTL Engineer to design and implement its digital blocks. The role owns RTL development from microarchitecture through synthesis-ready, timing-clean implementation and collaborates across design verification, physical design, DFT, and silicon bring-up.Strong digital-design fundamentals and expert…