ASIC Design Verification Engineer at Broadcom · Irvine, CA +2 more · Joined
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ASIC Design Verification Engineer
Broadcom · Irvine, CA +2 more · Just now · 0 applicants
NewOn-siteFull-timeLead
Pay
$129k–$207kListed
Workplace
On-site
Job type
Full-time
Level
Lead
Source: jobright · Posted by joined-scrapper
About the role
Broadcom seeks an experienced ASIC Design Verification Engineer to verify new silicon designs for Ethernet systems and support AI/ML acceleration. The role focuses on constrained-random verification, coverage closure, and SystemVerilog/UVM-based testbench development.
What you’ll do
Verify new ASIC designs for Ethernet systems
Develop innovative products that accelerate AI/ML workflows
Drive verification completion via coverage closure
Bachelor's degree and 12+ years of related experience, Master's and 10+ years, or PhD and 3+ years
Constrained random design verification experience
Experience driving verification to completion via coverage closure
SystemVerilog testbench structures (Class, SVA)
UVM, VCS, and Incisive expertise
Scripting skills (Python, Perl) and OOP knowledge
Original job description
Broadcom is a leading technology company specializing in silicon products for Ethernet systems. They are seeking a highly skilled ASIC Design Verification Engineer to verify new designs and develop innovative products that accelerate AI/ML workflows.Constrained Random Design Verification engineersexperience driving completion via coverage closure…