Senior ASIC DFT DV Engineer at Cisco · San Jose, CA · Joined
C
Senior ASIC DFT DV Engineer
Cisco · San Jose, CA · Just now · 0 applicants
NewHybridFull-timeSenior
Pay
$168k–$245kListed
Workplace
Hybrid
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
Cisco seeks a Senior ASIC DFT DV Engineer to plan and develop test benches that verify Design-for-Test architecture in silicon devices, collaborating with design, verification, and physical design teams to integrate, validate, and debug test logic.
What you’ll do
Plan and develop test benches to verify DFT architecture
Collaborate with design, verification, and physical design teams
Integrate and validate test logic
Develop reusable test and debug methodologies
Support silicon implementation and post-silicon validation
What you’ll need
Bachelor's in Electrical Engineering or equivalent with 7+ years (or Master's with 4+ years) of experience
Experience in test planning based on complex design specifications
Experience in testbench development using System Verilog
Experience debugging using DVE/Verdi
Experience with TCL, Python, or Perl
Knowledge of UVM, JTAG, scan architecture, MBIST, and boundary scan
Original job description
Cisco is hiring a Senior ASIC DFT DV Engineer to plan and develop test benches that verify Design-for-Test architecture for its silicon devices. The role collaborates with design, verification, and physical design teams to integrate and validate test logic, and develops reusable test and debug methodologies for silicon implementation and post-silicon…