Physical Design and Verification Engineer at Neuralink · South San Francisco, CA · Joined
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Physical Design and Verification Engineer
Neuralink · South San Francisco, CA · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
$131k–$265kListed
Workplace
On-site
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
Neuralink seeks a senior physical design engineer to own block-to-full-chip implementation and signoff for advanced-node multi-die 3DIC products, leading hierarchical physical design from RTL handoff through tapeout and developing multi-physics verification for stacked-die and chiplet-based systems.
What you’ll do
Own block-to-full-chip physical implementation and signoff
Lead hierarchical physical design from RTL handoff through tapeout
Develop multi-physics verification for stacked-die and chiplet systems
Perform STA and physical verification signoff
Handle large multi-million instance designs
Automate flows and analyze data with scripting
What you’ll need
BS/MS in Electrical/Computer Engineering or equivalent
5+ years of physical design experience
Full-cycle RTL-to-GDSII experience on advanced nodes
Hierarchical/top-level implementation on large designs
Strong STA concepts and physical verification signoff knowledge
Experience with 3DIC/2.5D/chiplet implementation and multi-physics analysis tools
Original job description
Neuralink is seeking a senior physical design engineer to own block-to-full-chip implementation and signoff for advanced-node, multi-die 3DIC products. The role leads hierarchical physical design from RTL handoff through tapeout and develops multi-physics verification for stacked-die and chiplet-based systems.BS/MS in Electrical/Computer Engineering (or…