Senior Physical Design and Timing Engineer at NVIDIA · Santa Clara, CA · Joined
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Senior Physical Design and Timing Engineer
NVIDIA · Santa Clara, CA · Just now · 0 applicants
NewHybridFull-timeSenior
Pay
$136k–$218kListed
Workplace
Hybrid
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
NVIDIA seeks a Senior Physical Design and Timing Engineer to drive physical design and timing closure for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs, supporting frontend and backend implementation from RTL to GDSII.
What you’ll do
Drive physical design and timing closure for high-performance chips
Support implementation from RTL to GDSII
Collaborate with frontend and backend teams
Improve power, performance, and area
Develop timing constraints and closure strategies
Automate optimization and signoff flows
What you’ll need
BS/MS in Electrical or Computer Engineering or equivalent
5+ years (BS) or 3+ years (MS) in physical design and timing
Experience with RTL-to-tapeout flows including synthesis, floorplanning, placement, CTS, routing, and ECOs
Proficiency in Static Timing Analysis and multi-mode multi-corner closure
Experience with EDA tools and scripting (Python, Tcl, Perl, Make)
Familiarity with AI/ML/DL/LLMs for automation
Original job description
NVIDIA is hiring a Senior Physical Design and Timing Engineer to drive physical design and timing for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs. The role supports frontend and backend implementation from RTL to GDSII and collaborates with multiple teams.BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of…