Design Verification Engineer at Reveille Technologies,Inc · United States · Joined
RT
Design Verification Engineer
Reveille Technologies,Inc · United States · Just now · 0 applicants
NewOn-siteFull-timeMiddle
Pay
Pay not listed
Workplace
On-site
Job type
Full-time
Level
Middle
Source: jobright · Posted by joined-scrapper
About the role
Reveille Technologies is hiring a Design Verification Engineer to verify IP, subsystem, and SoC designs. The role includes developing UVM/SystemVerilog verification environments, analyzing coverage and simulation results, and debugging with RTL designers.
What you’ll do
Verify IP, subsystem, and SoC designs
Develop UVM/SystemVerilog verification environments and tests
Analyze coverage and simulation results
Debug issues with RTL designers
Collaborate with design and validation teams
What you’ll need
Strong understanding of SystemVerilog and UVM
Good debugging skills
Understanding of AMBA protocols
Original job description
Reveille Technologies, Inc. is hiring a Design Verification Engineer to verify IP, subsystem, and SoC designs. The role involves developing UVM/SystemVerilog verification environments and tests, analyzing coverage and simulation results, debugging issues with RTL designers, and collaborating across design and validation teams.Strong understanding of SV…