About the role

What you’ll do

• Design, implement, and verify DFT features for server-class processors
• Collaborate with global teams and test engineering on ATE patterns, post-silicon bring-up, and debug
• Generate test plans, run simulations, and debug failures on RTL and Gate Level
• Optimize coverage and test time while addressing physical implementation and timing challenges
• Set up and run Scan DRC flows in RTL
• Lead efforts to derive cell-aware fault models and develop ATPG flows for silicon debug

What you’ll need

• Bachelor's in Electrical/Computer Engineering with 12+ years related experience, or Master's with 8+, or PhD with 5+
• Expert in MBIST design and implementation on repairable/non-repairable memories using electrical fuses
• Experience with EDT, SSN, IST, boundary scan, and JTAG/IJTAG features
• Hands-on experience with Siemens Tessent Shell flow or Synopsys SMS/SHS flow
• Proficiency in Verilog and scripting languages like Perl, Python, Shell, or Tcl
• In-depth experience in stuck-at, transition delay, and path delay coverage analysis

Original job description