Team: Accelerator IP · Source: jobright · Posted by joined-scrapper
About the role
Ericsson seeks a Senior RTL Design Engineer to own accelerator IP blocks from specification through delivery, optimizing power, area, and throughput for telecom hardware. The role requires deep ASIC design expertise and SystemVerilog mastery in a collaborative team environment.
What you’ll do
Own accelerator IP blocks from specification through delivery
Develop microarchitecture and RTL designs
Perform synthesis and timing closure
Optimize power, area, and throughput for telecom hardware
What you’ll need
Several years of RTL design in complex ASIC/IP environments
Proven ability to distill DSP, FEC, or other L1 processing algorithms into high-performance hardware
Comfortable deep-diving into code and shaping high-level architecture strategies
Collaborative and thrives in an intense, creative, close-knit environment
Original job description
Ericsson is hiring a Senior RTL Design Engineer for its Accelerator IP team. The role owns accelerator IP blocks from specification and microarchitecture through RTL design, synthesis, and delivery, while optimizing power, area, and throughput for telecom hardware.Several years of RTL design in complex ASIC/IP environmentsExpert SystemVerilog/Verilog…