Senior Digital Design Verification Engineer at Renesas Electronics · Austin, TX · Joined
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Senior Digital Design Verification Engineer
Renesas Electronics · Austin, TX · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
Pay not listed
Workplace
On-site
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
Senior Digital Design Verification Engineer to verify complex digital blocks and SoC features for power management products, owning the full verification lifecycle from planning to coverage closure, developing reusable SystemVerilog/UVM environments, and collaborating across cross-functional teams.
What you’ll do
Own verification from planning through coverage closure
Develop reusable SystemVerilog/UVM testbenches
Debug complex regression failures
Collaborate with architecture, design, firmware, analog, validation, and systems teams
Translate specifications into test plans, checkers, and coverage models
What you’ll need
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
4+ years of relevant digital design verification experience
Strong proficiency in SystemVerilog, UVM, and constrained random verification
Experience with functional coverage and SystemVerilog Assertions
Hands-on experience with Cadence and Synopsys verification tools
Experience with power management ICs, SoCs, or mixed-signal products
Original job description
Renesas Electronics is hiring a Senior Digital Design Verification Engineer to verify complex digital blocks and major SoC features for power management products. The role owns verification from planning through coverage closure, develops reusable SystemVerilog/UVM environments, debugs failures, and collaborates across architecture, design, firmware,…