This role leads the physical design organization for Amazon Annapurna Labs' custom ML accelerator SoCs, owning execution from RTL through GDSII, PPA optimization, and tapeouts across leading-edge nodes.
What you’ll do
Build and lead a physical design organization
Define execution strategies for advanced ML accelerator SoCs
Drive PPA and RTL-to-GDS methodology development
Lead tapeout execution
Coordinate with cross-functional teams, foundries, and EDA vendors
Manage hiring, performance, and organizational growth
What you’ll need
5+ years people management leading PD teams of 8+ engineers
10+ years hands-on ASIC/SoC physical design across 7nm, 5nm, and 3nm with multiple tapeouts
Full RTL-to-GDSII expertise including floorplanning, CTS, routing, timing closure, PDN design, and signoff
Mastery of Synopsys and Cadence EDA ecosystems with Calibre physical verification and TCL/Python/Perl scripting
Deep expertise in advanced STA (MMMC, POCV/AOCV) and power integrity (IR-drop, EM) plus low-power UPF design
Experience with AI/ML accelerator SoCs, 3nm GAA, and 2.5D/3D integration or chiplet strategies
Original job description
Amazon's Annapurna Labs designs custom silicon that powers AWS cloud infrastructure, including machine learning accelerator systems. The Senior Manager, Physical Design Engineering will build and lead a physical design organization, define execution strategies for advanced ML accelerator SoCs, drive PPA and RTL-to-GDS methodologies, lead tapeout execution,…