Design Verification Engineer at Cerebras · Sunnyvale, CA · Joined
C
Design Verification Engineer
Cerebras · Sunnyvale, CA · Just now · 0 applicants
NewOn-siteFull-timeMiddle
Pay
$190k–$230kListed
Workplace
On-site
Job type
Full-time
Level
Middle
Source: jobright · Posted by joined-scrapper
About the role
Develop verification strategies and reusable test environments for Cerebras' large-scale AI chips, debugging across simulation, emulation, and silicon bring-up while collaborating with hardware and software teams.
What you’ll do
Develop verification strategies
Create reusable test environments
Write tests and coverage plans
Debug issues across simulation, emulation, and silicon bring-up
Collaborate with cross-functional hardware and software teams
What you’ll need
Deep knowledge of SystemVerilog, DPI, and UVM
Excellent programming skills with object-oriented design
Experience with verification tools and methodologies (simulators, waveform viewers, automation, coverage, gate-level simulation)
Proficiency in scripting languages like Python or Perl
3-5+ years of Design Verification experience and knowledge of pipelined processor architecture
BS or MS in Computer Science or Electrical Engineering
Original job description
Cerebras Systems builds large-scale AI chips and infrastructure designed to accelerate AI training and inference. The Design Verification Engineer will develop verification strategies, reusable test environments, tests, and coverage plans, while debugging issues across simulation, emulation, and silicon bring-up and collaborating with cross-functional…