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Senior/Lead VLS Engineer - Global Circuits at SambaNova · San Jose, CA · Joined
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Senior/Lead VLS Engineer - Global Circuits

SambaNova · San Jose, CA · Just now · 0 applicants
NewOn-siteFull-timeLead
Pay
$210k–$280kListed
Workplace
On-site
Job type
Full-time
Level
Lead
Source: jobright · Posted by joined-scrapper

About the role

SambaNova seeks a Senior/Lead VLSI Design Engineer to architect and own global circuit areas, focusing on custom clocking, low-power design, and power distribution integrity. The role involves optimizing clock networks, performing power and signal-integrity analyses, and integrating PLL, IO, ESD, and latch-up strategies for SoC reliability.

What you’ll do

  • Architect and own global circuit areas including custom clocking and low-power design
  • Design and optimize clock distribution networks
  • Perform power and signal-integrity analyses
  • Integrate PLL, IO, ESD, and Latch-Up strategies for SoC reliability and performance
  • Ensure physical layout requirements for high-speed clocking and parasitic extraction
  • Bridge chip architecture with specialized IP deliverables

What you’ll need

  • Bachelor's or Master's degree in Electrical Engineering or Microelectronics
  • 8+ years of custom analog/mixed-signal VLSI design experience in advanced process nodes (FinFET/GAA)
  • Experience designing custom clock networks, low-power techniques, and custom IO/ESD/Latch-Up circuits
  • Deep knowledge of physical layout for high-speed clocking, parasitic extraction, and low-resistance interconnects
  • Strong cross-functional collaboration and technical communication skills
  • Deep familiarity with foundry ESD and Latch-Up design rules, guard-ring guidelines, and sign-off flows

Original job description

SambaNova is hiring a Senior/Lead VLSI Design Engineer to architect and own global circuit areas, including custom clocking, low-power design, and power distribution integrity. The role focuses on designing and optimizing clock distribution networks, performing power and signal-integrity analyses, and integrating PLL, IO, ESD, and Latch-Up strategies for…

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