Low Power ASIC Engineer - New College Grad 2027 at NVIDIA · Santa Clara, CA · Joined
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Low Power ASIC Engineer - New College Grad 2027
NVIDIA · Santa Clara, CA · Just now · 0 applicants
NewOn-siteFull-timeJunior
Pay
$100k–$167kListed
Workplace
On-site
Job type
Full-time
Level
Junior
Source: jobright · Posted by joined-scrapper
About the role
NVIDIA is hiring a new graduate Low Power ASIC Engineer to develop and verify power-management solutions for GPU and SoC products. The role involves collaborating with architecture, design, and software teams to build verification infrastructure and improve power-aware design verification.
What you’ll do
Develop and verify power-management solutions for GPU and SoC products
Collaborate with architecture, design, and software teams
Build verification testbenches, infrastructure, and test plans
Improve power-aware design verification methods
What you’ll need
BS, MS, or PhD in Electrical or Computer Engineering or equivalent experience
Understanding of low power design techniques such as multi VT, clock gating, power gating, block activity power, and DVFS
Good understanding of processor architecture; GPU knowledge a plus
Experience with Incisive Low-Power or Synopsys VCS NLP
Strong debug skills with Verdi; fluent in Verilog, SystemVerilog, and UVM
Knowledge of UPF, scripting in Python/PERL, C/C++, and Makefile experience a plus
Original job description
NVIDIA is hiring a Low Power ASIC Engineer to develop and verify power-management solutions for GPU and SoC products. The role works with architecture, design, and software teams to build verification testbenches, infrastructure, and test plans, and to improve power-aware design verification methods.Recently completed a BS, MS or PhD in Electrical or…