Applied ML - Functional Verification Engineer at Cadence · San Jose, CA · Joined
C
Applied ML - Functional Verification Engineer
Cadence · San Jose, CA · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
$154k–$286kListed
Workplace
On-site
Job type
Full-time
Level
Senior
Source: jobright · Posted by joined-scrapper
About the role
Cadence seeks a Senior Pre-Silicon Verification Engineer with deep functional verification expertise and a drive to apply AI to verification. The role involves debugging verification failures, using EDA tools, and programming in Verilog, SystemVerilog, and Python.
What you’ll do
Perform pre-silicon functional verification of ASIC designs
Leverage artificial intelligence to redefine verification processes
Debug verification failures using waveform viewers and simulation analysis tools
Apply verification methodologies such as Formal, SV/UVM, and OVM
What you’ll need
BS with 10+ years, MS with 7+ years, or PhD with 5+ years experience
3+ years of expertise in at least one pre-silicon ASIC verification methodology (Formal, SV/UVM, OVM)
Advanced debugging skills for pre-silicon verification failures using waveform viewers and simulation analysis tools
Hands-on experience with EDA tools like Jasper, Xcelium, and IMC
Strong programming skills in Verilog, SystemVerilog, and Python
Excellent communication, teamwork, self-motivation, and proactive problem-solving
Original job description
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. They are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification and a passion for leveraging artificial intelligence to redefine the verification landscape.BS with a minimum of 10…