ASIC Engineer, Design at Meta · Sunnyvale, CA · Joined
M
ASIC Engineer, Design
Meta · Sunnyvale, CA · Just now · 0 applicants
NewOn-siteFull-timeMiddle
Pay
Pay not listed
Workplace
On-site
Job type
Full-time
Level
Middle
Team: Infrastructure · Source: jobright · Posted by joined-scrapper
About the role
Meta is hiring an ASIC Design Engineer in its Infrastructure organization to develop custom ASICs for machine learning, video transcoding, and network acceleration. The role covers architecture exploration, micro-architecture development, IP integration, and design closure for timing and power.
What you’ll do
Architecture exploration
Micro-architecture development
IP integration
Collaborate with verification and emulation teams
Design closure for timing and power
What you’ll need
Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience
2+ years of experience in micro-architecture and RTL development for complex control and data path IPs
Experience in SoC micro-architecture, design and integration
RTL development using Verilog, System Verilog and HLS
Experience in CPU, NOC, memory and peripheral subsystems
Experience with synthesis, timing closure and formal verification methodology
Original job description
Meta is hiring ASIC Design Engineers within its Infrastructure organization to build cutting-edge ASICs for machine learning, video transcoding, and network acceleration. The role focuses on architecture exploration, micro-architecture development, IP integration, collaboration with verification and emulation teams, and design closure for timing and power.…