Senior ASIC Design Engineer - Memory Subsystem at NVIDIA · Santa Clara, CA · Joined
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Senior ASIC Design Engineer - Memory Subsystem
NVIDIA · Santa Clara, CA · Just now · 0 applicants
NewOn-siteFull-timeSenior
Pay
$136k–$218kListed
Workplace
On-site
Job type
Full-time
Level
Senior
Team: Memory Subsystem · Source: jobright · Posted by joined-scrapper
About the role
NVIDIA is hiring a Senior ASIC Design Engineer for its Memory Subsystem team, responsible for micro-architecture, RTL design, synthesis, and timing analysis. The role collaborates with architecture, verification, and physical design teams.
What you’ll do
Collaborate with architecture, verification, and physical design teams
Define micro-architecture for the memory subsystem
Develop RTL designs
Perform synthesis
Conduct timing analysis
What you’ll need
BS or MS in Electrical Engineering, Computer Engineering, or related degree (or equivalent experience)
5+ years of experience
Strong proficiency in Verilog or VHDL
Experience with scripting languages like PERL
Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, and system level caches is a plus
Experience with multiple clock domains, asynchronous interfaces, and industry specifications like CHI/CXL/PCI-E is a plus
Original job description
NVIDIA is hiring a Senior ASIC Design Engineer for its Memory Subsystem team. The role collaborates across architecture, verification, and physical design teams, and is responsible for micro-architecture and design, including RTL design, synthesis, and timing analysis.BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent…